But to work as a whole, they require to co-operate constantly. So far I’ve talked about how the two CPUs work individually. I guess with hardware like this, it’s easy to figure out the real reason kids loved this console, eh? Interconnection So programmers will have to manually maintain memory consistency by flushing the write-buffer before triggering DMA, for instance. Cache and DMA can provide a lot of performance but also create new problems, such as data integrity.Combined with the use of cache, both CPU and DMA can potentially work concurrently. A Direct Memory Access Controller: Accelerates memory transfers without depending on the CPU.A Divisor and Square root unit to speed up these types of operations (the ARM9 by itself is not capable of performing this type of math).Nintendo also added the following components around it: 48 KB of Tightly-Coupled Memory or ‘TCM’: Similar to Scratchpad memory, however this one discriminates between instructions (32 KB) and data (16 KB).12 KB of L1 Cache: The core now features cache, where 8 KB are allocated for instructions and 4 KB for data.5-stage Pipeline: This is another increment from the previous 3-stage pipeline.If you take a look at the core name, the letter ‘E’ means Enhanced DSP which implies that lots of these new instructions have to do with applications for signal processing.The ARMv5TE ISA: Compared to the previous v4, features some new instructions and a faster multiplier.Part of the ARM9 series, this core in particular not only inherits all the features of the ARM7TDMI but also includes some additional bits : If you ignore the ill-fated ARM8 series, you could say the ARM946E-S is the ‘next-gen’ version of the ARM7. Here is the ‘main’ CPU of the Nintendo DS running at ~67 MHz. That being said, let’s take a look now at the two CPUs: This design methodology is called Asymmetric multiprocessing and the resulting CPUs’ co-dependency will condition the overall performance of this console. The Nintendo DS includes two very independent computers that will perform exclusive operations, each one having a dedicated bus. For instance, we are not talking about the ‘experimental’ master-slave configuration that the Saturn debuted or the ‘co-processor’ approach found on the PS1 or N64. While this is not the first parallel system analysed for this series, its design is very different from the rest. So, their functioning may be considered a bit unorthodox taking into account the present technology available. Now, CPU NTR implements an interesting multi-processor architecture using two different ARM CPUs, this design was done before ARM Holdings officially released multi-processor solutions. ‘NTR’ is shorthand for ‘Nitro’, the codename of the original Nintendo DS. There will be some innovation and a few compromises, but this combination may pave the way for new and ingenious content.Īs with Nintendo’s previous portable console, the system revolves around a big chip named CPU NTR. This console is an interesting answer to many needs that weren’t possible to fulfil in the handheld ecosystem. ![]() If you have trouble following the components: Top is only accessed by ARM9, bottom section is ARM7-only, middle section is shared. Motherboard with important parts labelled Diagram Main architecture diagram The profits contribute towards the improvement of current articles and the development of future ones.įor more information, please take a look at here. You can find the eBook at Amazon Kindle, Apple Books, Kobo and other stores. Furthermore, it's updated at the same pace as the website. The new edition is DRM-free and can be read whilst offline. This article is also published on many digital book stores for the benefit of eBook readers.
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